Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors

The main design principles in computer architecture have recently shifted from a monolithic scaling-driven approach to the development of heterogeneous architectures that tightly co-integrate multiple specialized processor and memory chiplets. In such data-hungry multi-chip architectures, current Networksin- Package (NiPs) may not be enough to cater to their heterogeneous and fast-changing communication demands. This position paper makes the case for wireless in-package networking as the enabler of efficient and versatile wired-wireless interconnect fabrics for massive heterogeneous processors. To that end, the use of graphene-based antennas and transceivers with unique frequency-beam reconfigurability in the terahertz band is proposed. The feasibility of such a wireless vision and the main research challenges towards its realization are analyzed from the technological, communications, and computer architecture perspectives

High density emerging resistive memories: What are the limits?

International audienceWith the saturation of the Flash memory technologies scaling under the 20nm nodes, new technology opportunities are explored by both industrial and academic research teams. Resistive switching memories are today seen as the most promising replacement candidate for both embedded (NOR) and stand-alone (NAND) flash memories. The native Back-End-of-Line (BEoL) integration enabled by the RRAM technologies opens the way for new 3D architectures such as crosspoint or Vertical-RRAM, and triggers the development of novel BEoL selection devices. These architectures bring new design challenges, for instance, sneaking currents through unselected bitcells (SneakPaths), voltage drop along deeply scaled (< 50nm) metal lines (IRdrop) and peripheral circuitry overhead. In this paper, we introduce two physical IRdrop models for crosspoint and Vertical-RRAM architectures. We also introduce a peripheral circuitry model for crosspoint architecture. Using these models, we show that both periphery overhead and IRdrop limit the crosspoint architecture under 50nm of half pitch

Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination

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Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop

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Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays

International audienceEnergy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages and resistance levels. The programming conditions of memory elements (e.g. pulse widths and amplitudes) must cover the tail bits to avoid programming failures. Switching time of ReRAMs shows wide distributions. Therefore, fast cells are subjects for electrical stress after their switching and energy waste since programming currents are typically large for this technology (tens of µA). In this paper, we present a Write Termination (WT) circuit to stop the programming operation when the switching event occurs in the selected memory element. The proposed design is sensitive to current variations that take place when the memory element switches between two different resistance states (LRS and HRS). This WT scheme reduces the power consumption by 97+%, 93+% and 65+% during Forming, RESET and SET operations respectively. Our estimations show that area efficiency of 70% for a memory array is achievable when the presented WT circuit is integrated in near-memory peripheries. The demonstrated WT circuit is suitable for different ReRAM technologies with small overhead penalty and shows robustness against CMOS and ReRAM variabilities

New perspectives for multicore architectures using advanced technologies

International audienceImpact of advanced technologies on the design and structure of multicore architectures is presented in this paper. More specifically, the power consumption and design complexity walls are examined leading to a “conquer-and-divide” strategy based on multicore partitioning and specialization. We then show how 3D stacking, Monolithic 3D integration and BEOL NVM can be associated to build new, simplified and power- efficient multicore

In-depth investigation of programming and reading operations in RRAM cells integrated with Ovonic Threshold Switching (OTS) selectors

International audienceThis paper presents an HfO2 based resistive switching memory (RRAM) in series with a GeSe-based Ovonic Threshold Switching (OTS) selector. Detailed investigation of the main memory operations, forming, set, reset and read is presented for the first time to our knowledge. An innovative reading strategy is proposed. The selector switching is performed only if the RRAM cell is in the Low Resistive State (LRS), while the reading of the High Resistive State (HRS) is performed without switching the OTS selector, preventing disruptive reading when the RRAM cell is in HRS. Up to 106 read cycles have been demonstrated with a stable memory window of one decade and a stable OTS OFF state

Functionality and reliability of resistive RAM (RRAM) for non-volatile memory applications

International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, TAIWAN, APR 25-27, 2016International audienceVarious RRAM concepts are currently being investigated (Oxide based RAM, Conductive Bridge RAM), all showing pros and cons depending on the architecture and memory stack. As the specifications are strongly application-dependent, it is likely that the RRAM technology will be bound to a specific market segment. In this paper, we discuss the potential of RRAM for non-volatile memory applications, among them: storage class memory, embedded memory, programmable logic, mass storage and neuromorphic applications. By means of experimental studies and simulations, we analyze the role of the integrated materials on the memory performances and reliability and try to propose optimized stacks suitable for each targeted application

Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives

International audienceIn this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then 2 potential applications are discussed using design approach. For high density, the Vertical RRAM cell features and circuit are dimensioned to optimize the memory page density. Finally, for neuromorphic applications, selector and array configuration are tuned to reduce the variability in terms of voltage seen by each cell constituting a vertical synapse